This invention relates to a semiconductor manufacturing process and more specifically relates to a process for forming a low resistance titanium silicide layer atop a polysilicon layer to reduce the lateral resistance of the polysilicon layer.
Semiconductor devices, such as power MOSFETs, IGBTs, and the like commonly have thin layers of polysilicon used, for example, as gate electrodes. It is desirable to reduce the lateral resistance of these polysilicon layers and they are commonly doped by impurities such as phosphorous to increase their conductivity. It is also known to further coat the top of the polysilicon layer with a titanium silicide layer of low resistivity.
To obtain this low resistivity titanium silicide layer, a two-step rapid thermal anneal (RTA) process, each at temperature less than about 750xc2x0 C., is used. The thermal processing should be a temperature less than about 800xc2x0 C. at which contamination diffusion begins. However, the underlying silicon remains completely clean if the RTA temperature is no greater than 625xc2x0 C. The use of titanium silicide for this purpose is described in the following: J. Lutze, G. Scott, and M. Manley, xe2x80x9cTransistor off-state leakage current induced by TiSi2 pre-amorphizing implant in a 0.20 um CMOS process,xe2x80x9d IEEE Trans. Electron Device Lett., vol. 20, p. 155, April 2000; Qingfeng Wang, xe2x80x9cTiSi2 and CoSi2 SALICIDE Technology and their Application in CMOS,xe2x80x9d Advanced Process Technology Seminar, AG Associates, Jun. 20 and 21, 1996; J. F. DiGregorio and R. N. Wall, xe2x80x9cSmall Area Versus Narrow Line Width Effects on the C49 to C54 Transformation of TiSi2,xe2x80x9d IEEE Trans. Electron Devices, vol. 47, p. 313, February 2000; C. Y. Chang and S. M. Sze, xe2x80x9cULSI Technology,xe2x80x9d The McGraw-Hill Companies, Inc., 1996, ISBN 0-07-063062-3; and S. P. Murarka, xe2x80x9cSilicide for VLSI Applications,xe2x80x9d Academic Press, Inc., 1983, ISBN 0-12-11220-3.
It would be desirable to deposit a low resistivity layer of titanium silicide on polysilicon using a single RTA step.
In accordance with the invention, a titanium silicide layer is formed atop a polysilicon layer surface with a single low temperature (under 650xc2x0 C.) RTA step. Thus, an intermediate amorphous silicon layer is first formed atop the polysilicon. Titanium is then sputtered atop the amorphous silicon layer, and a single RTA step is carried out at about 625xc2x0 C. for about 30 seconds, followed by a titanium wet strip, producing the desired low resistivity titanium silicide layer intimately bonded to the polysilicon layer.